Test Patterns Compression Techniques Based on Sat Solving for Scan-based Digital Circuits

In the paper we propose a new method of test patterns compression based on SAT (SATisfiability) solving. By test patterns compression we can dramatically decrease test memory requirements for test patterns storing. This compression method is very suitable for scan-based digital circuits. Test patterns are decompressed in the scan chain during the test, no additional hardware is required. By this way we can also decrease the data bandwidth between ATE (Automatic Test Equipment) and the internal test mechanism. The main idea is based on test patterns overlapping introduced in the COMPAS (COMpressed Pattern Sequencer) compression tool [1]. Our proposed algorithm is based, as well as COMPAS, on patterns overlapping. During the test generation, we are trying to efficiently generate vectors as candidates for an overlap, unlike COMPAS, which is based on efficient overlapping of pre-generated test patterns. We introduce our basic algorithm and show results obtained for standard ISCAS’85 and ‘89 benchmark circuits. The results are compared with the COMPAS compression tool.